Shadow mask and method for producing a shadow mask

ABSTRACT

The disclosed device is directed towards a shadow mask for ion beams comprising a silicon wafer with a hole pattern arranged therein, wherein the silicon wafer is provided at a side confronting the incident ion beams with a metallic coating which stops the ion beams and dissipates heat, wherein an apertured region of the silicon wafer has a thickness from about 20 μm to about 200 μm and apertures in the shadow mask have lateral dimensions from about 0.5 μm to about 3 μm.

The present invention relates to a shadow mask, in particular to ashadow mask for ion beams or ionized molecular beams, comprising asilicon wafer with a hole pattern arranged therein, the inventionfurthermore relates to a method for the manufacture of such a shadowmask.

Shadow masks of the initially named kind and also methods for theirmanufacture and certain applications of the same are known from U.S.Pat. No. 5,672,449. The silicon wafers there are relatively thin withthicknesses below 10 μm which are for example used for lithographicpurposes. The ion beams which are used here have very small powers, forexample up to about 10 Milliwatts.

It is also known to carry out a structuring of a substrate by means ofion. beams by the application of a contact mask. The customarystructuring through the application of a contact mask on a substratehowever fails if the substrate is strongly heated during theimplantation or if the introduced ion doses are very high. Ion beamswith large penetration depths can also not be structured in this mannerin the sub-micrometer range. One known solution of this problem is toseparate the mask and the substrate. This takes place for example by theion projection in that the ion beams are guided through a diaphragm orshadow mask and are imaged onto a substrate by means of a suitable lens.Examples of these methods are the patents no. DE 19633320 A1 and DE2702445 A1. In both methods the previous mask technology is however notsuitable for blending out ion beams of high power density. The previousion projection methods (patent no. DE 19633320 A1) are thus restrictedto ion beams of low power density. These masks are destroyed in a shorttime by ion beams of high power density.

The present invention relates, in contrast, to shadow masks, methods ofusing shadow masks and applications of shadow masks which can be usedwith particle beams of all kinds, for example ions with comparativelyhigh power densities in the order of magnitude of some watts/cm_ or morein order to structure substrates of the most diverse kind rapidly underhigh doses and with sharp edges and in order to implant ions intosubstrates.

The sharp-edged structuring of substrates signifies here for example theability to produce structures with a resolution smaller than 3 μm on anarea larger than 1 mm_.

The object of the present invention is to present such shadow masks andalso methods for their manufacture and uses which are suitable for usewith particle beams and ion beams with relatively high power densities,for example in order to blend out ion beams with power densities in theabove-mentioned order of magnitude and nevertheless to attain adurability of the shadow masks of more than 100 operating hours.

In order to satisfy this object provision is made, in accordance withthe invention, that the silicon disk has, at the side confronting theincident ion beams, a metal coating which stops the ion beams anddissipates heat. Through this metal coating the ions are, on the onehand, stopped in an effective manner and the kinetic energy of the ionbeams is converted into heat, with the metallic coating, ensuring, as aresult of its thermal conductivity, the required thermal dissipation.

Should the thermal dissipation not suffice in order to ensure thedesired long life of the shadow mask then, in accordance with theinvention, a diamond layer can be inserted between the metal coating andthe silicon wafer and the thickness of this layer can for example liebetween 2 μm and 10 μm. Diamond has, namely, an excellent thermalconductivity. Another possibility, which can optionally also be used incombination with the diamond layer, lies in working cooling passagesinto the silicon wafer and/or into the diamond layer and/or into themetal of coating, with the cooling passages being used to conduct acooling fluid, in particular a cooling gas, for example helium, andcorrespondingly having to be covered over, for example by the metalcoating, so that closed cooling passages are present. The coolingpassages must however be provided with an inlet and an outlet whichenable the supply and discharge of the fluid or gas used for thecooling. Even if the inlet and the outlet are likewise closed during theclosing of the passages they can be straightforwardly freed again byspark erosion, or by other methods, so that the required connections canbe applied there. The inlets and the outlets can be arranged at thefront side of the shadow mask (i.e. at the side where the ions areincident), at the rear side or at the side edge of the apertured wafer.

The cooling passages can for example have a width in the range between100 nm and 10 μm and a depth of up to 80% of the total thickness of theshadow mask. It is particularly favourable when using cooling passagesthat these can be matched in their distribution, density, width anddepth to the local heat generation. I.e. in regions of the shadow maskwith a smaller hole cross-sectional area per unit of surface area, andthus a larger heat generation as a result of the ion beams that arestopped, more heat can be dissipated by corresponding design of thecooling passages, so that a uniform temperature or a desired or also amerely acceptable temperature distribution can be achieved over thetotal area of the shadow mask.

The invention further comprises a method for the manufacture of sharpedged structures by particle beams of high power densities >1 W/cm_. Inthis way a rapid implantation and modification of smaller structures orthe implantation of higher doses is possible.

In this connection a shadow mask is used with a diameter >1 mm_ whichsatisfies the above-named requirement with respect to stability,material, removal and thermal transport. The shadow mask can bestructured in any desired manner and has a lateral resolution <3 μm. Inconjunction with an image forming system structures of the mask can betransferred in reduced size onto a substrate, with the mask and thesubstrate being spatially separated. Through this apparatus acontamination of the substrate with mask material is prevented.

Substrates having surfaces of any desired shape can be implanted.

The substrate, with a surface of any desired shape, can be heated tohigh temperatures during the implantation, in order, for example, toavoid crystal damage. The applications which result from this are forexample sensors on tips with a high lateral resolution or miniaturepressure stamps with structures below one micrometer for the marking ofany desired articles in a manner secure against forgery.

The invention thus relates to a method of structuring substrates withparticle beams, for example ions, of high power density rapidly and withhigh doses in a sharp edged manner, with a shadow mask being used havingstructures with smaller than 3 μm resolution on an area >1 mm_.

The shadow mask is suitable for blending out ion beams with powerdensities of >3 W/cm_ and has a durability of more than 100 hours.

The maximum energy density results from the multiplication of the ionenergy and the ion current density with which the mask is irradiated atany desired point in time. This invention thus permits both high beamcurrent densities and also ion beams of high energy to be blended out.

The form of the ion beam striking the sample is defined at the mask bythe stopping of any associated regions of the ion beam in the maskmaterial located in the beam path. The ion beam can pass unhinderedthrough the open regions of the mask, i.e. is not scattered. In order toachieve good image forming characteristics the ion beam must radiatethrough the mask in approximately parallel manner. The edges of the maskstructures must have very small negative edge inclinations to avoidscattering, i.e. the deflection of the ions from their flight path bycollision processes with particles of the mask or transparent zones,i.e. regions of the mask in which the ions loose energy and aredeflected but can still strike the sample. The side of the maskconfronting the incident ion beam stops the ions during the period ofdurability without being destroyed during this time by the incidence ofthe ions or by the stopped ions. The energy introduced during stoppingof the ions is led away through the mask material to a heat sink orcooling system. The thermal dissipation is so designed that a change intemperature of the mask does not impair the resolution of the imageformation.

If the mask is additionally transferred by particle radiation by meansof a lens onto a substrate then the structures can be projected to besmaller or larger by the factor set by the image formation.

The structural resolution achievable in this apparatus results from thestructural sizes of the mask divided by the amount of the reduction oramplification V. The edge sharpness which can be achieved is restrictedby the thermal expansion of the mask during the radiation divided by Vand by the image forming error.

The advantage of such an apparatus is that the substrate and the maskcan be spatially separated from one another, in dependence on the imageformation, and contamination can be avoided by mask material removed bythe ion beam. The substrate can be heated during the implantation tohigh temperatures without destroying the mask. Furthermore high dosesand ions of high penetration depth can be implanted in structured mannerinto a substrate which would not be possible with customary contactmasking.

The provision of masks in accordance with the invention and having thesecharacteristics opens up the possibility of manufacturing novelmaterials by structured implantation and of structuring materials underconditions which would prohibit an otherwise customary contact masking.

The invention will be explained in more detail in the following withreference to embodiments and to the accompanying drawing in which areshown.

FIGS. 1A–1K an embodiment of the method of the invention by way ofexample,

FIGS. 2A–2C a schematic representation of an embodiment for a mask inaccordance with the invention with integrated cooling passages, and

FIG. 3 a photographic reproduction of an embodiment of a shadow mask inaccordance with the invention.

FIG. 1A shows here a (100) silicon wafer 10 with a specific resistanceof 0.01 Ohm cm and is polished on both sides. By way of example thewafer 10 of FIG. 1A has a thickness of 500 μm and a width of 100 mm. Inplane view (not shown) the silicon wafer is circular in this embodimentwith a customary flat at one position.

The silicon wafer 10 of FIG. 1A is coated by means of an oxidation stepat at least substantially all surfaces with SiO₂, so that, for example,a 2 μm thick SiO₂ arises, as shown at 12 in FIG. 1B. The thickness ofthis coating 12 can, for example, straightforwardly lie in the rangebetween 100 nm to 5 μm or more. Such layers can be produced by wetoxidation at 1150° C. Wet signifies here that water is introduced intothe treatment chamber.

As FIG. 1C shows the SiO₂ coating 12 is removed at a part region 14 ofthe rear side of the wafer. This removal can for example take place by alithographic process. By immersing the wafer into an alkaline solutionit is then etched from the rear side, as shown in FIG. 1D, so that acentral region 16 of the wafer arises which is thinner in comparisonwith the marginal region 18, where the SiO₂ coating 12 is stillmaintained. This region 16 can for example have a thickness of 200 to300 μm.

Next of all the front side 20 of the wafer is coated with a resistmaterial 22, as shown in FIG. 1E. This is subsequently exposed anddeveloped in order to provide the resist layer 22 with a pattern bymeans of lithography which reproduces the shape of the desired holes ofthe shadow mask.

After carrying out an oxide etching process and removal of the resistcoating 22 holes 24 are present in accordance with the desired holepattern in the SiO₂ layer 12 in the thinned region 16, as shown in FIG.1F.

The wafer is now treated by means of an etching process, for example inthe form of a dry etching process such as reactive ion etching, sputteretching or etching with alternating gas types (so called gas chopping),in order to produce the hole pattern which is present in the SiO₂ layeralso in the thinned region 16 of the apertured wafer. The correspondingholes are designated in FIG. 1G by 26.

Thereafter the wafer is subsequently oxidized, as shown in FIG. 1H, inorder to provide the regions freed of SiO₂ in the etching step of FIG.1F, including the inner walls of the holes 26, with SiO₂ 12, i.e. SiO₂is formed on all surfaces of the wafer.

The method step of FIG. 1H can also be carried out by wet oxidation at1150° C.

Through this method it is ensured, through the insulating SiO₂ layerwhich has arisen in this way, that the surfaces coated with SiO₂ 12 arenot covered over by galvanically deposited metal during a subsequentgalvanic coating step. It is however desired to build up a galvanicmetal coating 28 of the front side 20 of the wafer (FIG. 1J) which iswhy the SiO₂ layer 12 is removed from this front side 16 in accordancewith FIG. 11. This can take place by an etching process but also by amechanical process such as CMP (Chemical Mechanical Polishing) or inother ways.

A starting layer, which is not shown in the drawing, is now formed onthe exposed front side of the wafer. For example, a starting layerconsisting of GeO, Cr or of another metal or of a highly conductivesemiconductor layer, such as for example highly conductive silicon, isapplied, for example by a sputter treatment, and the wafer is thenintroduced into a galvanic bath where, after appropriate contacting ofthe starting layer, the metal layer 28 is applied galvanically to thefront side of the silicon wafer with a thickness in the range between0.5 μm and 20 μm, as is indicated in FIG. 1J. The purpose of thisstarting layer is to make the surface of the wafer conductive, so thatthe galvanic process can be carried out.

After the formation of the galvanic layer 28 the SiO₂ layer 12 isremoved at all surface regions by an etching process and the wafer,which now represents the desired shadow mask, is subsequently clean. Thereason for the removal of the SiO₂ layer 12 in FIG. 1J lies in the factthat the insulating action would otherwise lead to an undesired chargingup of the shadow mask on bombardment with ions. The shadow mask is thento be seen as illustrated in FIG. 1K, with the hole pattern 30 forexample being formed in similar manner to FIG. 3.

The precise geometrical shape of the hole pattern 30 present in theshadow mask is in principle not of importance, it must be designed inaccordance with the envisaged purpose. It is sufficient here to bringout that the above described method and also the modifications of themethods described below make it possible to provide shadow masks withfiligrane holes, which can be used for a plurality of purposes. It is inparticular possible to provide the holes with length and/or widthdimensions which are smaller than 3 μm, whereby correspondingly finestructures can be produced in a substrate which is bombarded with ionbeams through the mask.

When the mask is held removed from the surface of the substrate and anion beam is projected onto the mask, so that a reduced image of the holepattern is produced on the substrate, whereby very many fine structurescan be realized, since it is nowadays straightforwardly possible tooperate with size reduction factors of up to 100.

A series of modifications of the just described method are possible. Forexample the steps of FIGS. 1B, 1C and 1D can be omitted, i.e. it is notessential to treat the wafer in order to provide a thinned centralregion 12 and a thicker marginal region 18. Instead of this it isentirely possible to dispense with such a thinning operation on choosingsuitable dimensions for the apertured wafer, above all a thickness inthe range from 300 μm upwardly. The sense of the marginal region 18 isultimately only to obtain a stable wafer which is easy to handle. If thewafer 10 is made thicker then it is not necessary to thin it at thecentre.

When the steps of FIGS. 1B to 1D are omitted then the wafer looks, inthe illustration of FIG. 1E approximately as it does in FIG. 1A but withan SiO₂ layer at at least the front side, which can for example also beproduced by a sputtering process. The further treatment of the waferthen proceeds as shown in FIGS. 1F to 1K.

A further modification with respect to the methodology of FIG. 1 lies indepositing a diamond layer under the surface of the silicon wafer usinga methodology known per se. This can for example be carried out directlyafter the step a) or after the step i) and other possibilities are alsoconceivable. The diamond layer is for example realized with a thicknessin the range between 2 μm and 10 μm and has a very high conductivity. Itthus serves for a rapid dissipation of heat from hot regions of themetal layer, i.e. regions where relatively many ions are stopped andensures that the shadow mask has a uniform low temperature, whereby theworking life of the shadow mask can be increased. Another possibility ofimproving the heat dissipation lies in producing cooling passages in theapertured wafer through which cooling gases, above all helium can bepumped in order to remove heat from the wafer and hereby reduce thetemperature of the apertured wafer and increase its working life. Asshown in FIG. 2A the cooling passages 30 can be worked into the siliconwafer itself and they are respectively provided with an inlet 32 and anoutlet 34 in order to enable the supply and discharge of the coolinggas. One possibility of realizing the cooling passages lies in producingthem with a lithographic process. Such cooling passages could forexample be produced prior to or after the method step of FIG. 11. AsFIG. 2B shows the cooling passages can have a considerable depth, theycan for example have a depth of up to more than 80% of the totalthickness of the apertured wafer 16 and they could also vary in depthand/or width and/or length in order to adapt the locally present coolingsurface area to the respective circumstances, i.e. the passages can havea larger area at places where heat has to be dissipated, so that theheat transfer from the apertured wafer to the cooling gas is improved.

The open passages 30 shown in FIGS. 2A and 2B must be closed. This takesplace best of all in that the apertured wafer is closed by a metal in atilted position by means of vapour deposition or sputtering. Theapertured wafer is rotated in the tilted position and this leads to theopenings to the passages being rapidly closed, in particular when thecooling passages are made relatively narrow as shown in FIG. 2C. As soonas the passages have been closed at the top the apertured wafer can beintroduced into the galvanic bath in order to grow the desired galvaniccoating 28 on the surface of the apertured wafer.

The vapour deposition or sputtering of metals onto the surface of theapertured wafer in order to close cooling passages can namelysimultaneously serve to deposit a metallic starting layer for thegalvanic coating on the surface of the apertured wafer.

Another possibility of introducing the cooling passages into theapertured wafer lies in lithographically producing the cooling passagesalready at the stage of FIG. 1A. The apertured wafer can then beintroduced before further steps into a sputtering device and treatedwith a material, for example silicon dioxide or silicone nitrite in asputtering process, so that the cooling passages are closed from thetop. In such a treatment it is necessary to arrange the wafer at anoblique angle and to rotate it. The covering over of the coolingpassages can only take place economically with this oblique angle. Afterthe covering over of the cooling passages in this way and means thewafer can be polished by means of CMP. In this way the irregularitiesproduced by the sputtering process are removed, however the polishingprocess is carried out so that the cover for the cooling passages is notbroken through. The method then proceed as previously described inconnection with FIG. 1, optionally omitting the method steps of FIGS.1B, 1C and 1D, until the stage of FIG. 1I is achieved.

It is now necessary to once again close the (now reopened) coolingpassages by sputtering. For this purpose the apertured wafer isintroduced into a sputtering apparatus and rotated in an obliqueposition so that the entrances to the cooling passages are closed overwith a metallic coating. The surface at the front side of the wafer isalso provided with the metallic coating and this then serves as astarting layer for the galvanic coating. It is indeed possible that theholes of the shadow mask which form the actual hole pattern are alsoclosed by this process. This is however not problematic, because it ispossible to bombard the holes of the hole pattern with ions from therear side, whereby the hole pattern can be laid free again. Thebombarding of the rear side of the apertured wafer with ions does nothave any disadvantageous effect on the cooling passages, since these areclosed from below, so that the ions cannot enter into action there.After deposition of the galvanic coating the SiO₂ coating can be removedas previously and the shadow mask presents itself in the finished statein accordance with FIG. 1K.

It is also possible to design the cooling passages so that they alsoextend through any diamond layer that is present. In order to bring thisabout, the diamond layer can either be deposited onto the surface of theapertured wafer when the cooling passages are already present but havenot yet been closed, or the entire surface of the apertured wafer can beprovided with a diamond layer and a lithographic process can be used inorder to form the cooling passages. For example one can irradiate thediamond layer with an ion beam in order to convert it locally intographite and this graphite layer can then be easily etched away.

The cooling passages can also be present in the metal layer. It is forexample possible to deposit a part of the metal layer, then to producecooling passages in the metal layer, for example by means of alithographic method and then to close off the cooling passages and growa further metal layer by means of a galvanic process on the existingmetal layer, in order to finish the metal layer.

The metal layer can also consist of an alternating sequence of differentmetal layers which have different lattice constants. The latticeconstant of the one layer should be smaller than that of silicon whereasthe lattice constant of the other layer should be larger than that ofsilicon so that on average no strain is present. Intermediate layers canbe provided at the transition between the silicon wafer and the firstmetal layer of the alternating layer sequence which achieves a gradualadaptation to the lattice constant of the lowermost metal layer so thaton the whole a structure without pronounced strain is present.

1. Shadow mask for ion beams consisting of a silicon wafer with a holepattern arranged therein, wherein the silicon wafer is provided at theside confronting the incident ion beams with a metallic coating whichstops the ion beams and dissipates heat, characterized in that theapertured region of the silicon wafer has a thickness in the range from20 μm to 200 μm and in that the apertures in the shadow mask havesmallest lateral dimensions in the range between 3 μm and 0.5 μm. 2.Shadow mask in accordance with claim 1, characterized in that a diamondlayer is located between the metal coating and the silicon wafer. 3.Shadow mask in accordance with claim 2, characterized in that thediamond layer has a thickness between 2 μm and 10 μm.
 4. Shadow mask inaccordance with one of the preceding claims, characterized in that thesilicon wafer has a thicker marginal region in comparison to theapertured region.
 5. Shadow mask in accordance with one of the precedingclaims, characterized in that the marginal region of the apertured waferhas a thickness in the range between 300 μm and 1000 μm.
 6. Shadow maskin accordance with one of the preceding claims, characterized in thatthe metal coating consists of one or more of the following metals: W,Ti, Au, Mo, Co, Cu, Hf, Al, Ta, Cr, Pt, Ag.
 7. Shadow mask in accordancewith one of the preceding claims, characterized in that the thickness ofthe metal coating lies in the range between 0.5 μm and 20 μm.
 8. Shadowmask in accordance with one of the preceding claims, characterized inthat the metal coating consists of an alternating layer sequence ofdifferent metals or compositions with different lattice constants largerand smaller than silicon in order to avoid larger strains.
 9. Shadowmask in accordance with one of the preceding claims, characterized inthat cooling passages are worked into the silicon wafer and/or into thediamond layer and/or into the metal coating and are covered over by themetal coating.
 10. Shadow mask in accordance with claim 9, characterizedin that the cooling passages are provided with an inlet and with anoutlet which are not are not fully covered over by the coating. 11.Shadow mask in accordance with one of the claims 9 or 10, characterizedin that the cooling passages have a width in the range between 100 nmand 10 μm and a depth of up to 80% of the total thickness of the shadowmask.
 12. Shadow mask in accordance with one of the preceding claims,characterized in that the wafer has an outer diameter in the rangebetween 5 mm and 300 m or more.
 13. Shadow mask in accordance with oneof the preceding claims, characterized in that with ion beams with powerdensities greater than 3 W/cm² the shadow mask has a durability of over100 hours.
 14. Shadow mask in accordance with one of the precedingclaims, characterized in that the walls which bound the holes of theshadow mask at least partly diverge in the direction away from the metalcoating.
 15. Shadow mask in accordance with one of the preceding claims,characterized in that the metal coating of the shadow mask is providedwith an electrical voltage connection.